AT32AP7001-ALUT Atmel, AT32AP7001-ALUT Datasheet - Page 626

• Manufacturer Part Number: AT32AP7001-ALUT
• Description: IC MCU 32BIT AVR32 208-LQFP
• Manufacturer: Atmel
• Series: AVR®32 AP7r

Specifications of AT32AP7001-ALUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, I²C, MMC, PS2, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²C, POR, PWM, WDT
• Number Of I /o: 90
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: D/A 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-LQFP
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, ISI, MCI, PS2, SPI, TWI, USB
• Maximum Clock Frequency: 150 MHz
• Number Of Programmable I/os: 90
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Dac: 16 bit, 1 Channel
• Package: 208PQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 150 MHz
• Operating Supply Voltage: 1.8 V
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATNGW100 - KIT AVR32 NETWORK GATEWAYATSTK1000 - KIT STARTER FOR AVR32AP7000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

32.6.10.2
32.6.10.3
32.6.10.4
32.6.10.5
32.6.10.6
32015G–AVR32–09/09
From Powered State to Default State (Reset)
From Default State to Address State (Address Assigned)
From Address State to Configured State (Device Configured)
Entering Suspend State (Bus Activity)
Receiving a Host Resume
The wake-up feature is not mandatory for all devices and must be negotiated with the host.
After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmasked
flag ENDRESET is set in the IEN register and an interrupt is triggered.
Once the ENDRESET interrupt has been triggered, the device enters Default State. In this state,
the USBA software must:
• Enable the default endpoint, setting the EPT_ENABL flag in the EPTCTLENB[0] register and,
• Configure the Interrupt Mask Register which has been reset by the USB reset detection
• Enable the transceiver.
In this state, the EN_USBA bit in CTRL register must be enabled.
After a Set Address standard device request, the USB host peripheral enters the address state.
Warning: before the device enters address state, it must achieve the Status IN transaction of
the control transfer, i.e., the USBA device sets its new address once the TX_COMPLT flag in the
EPTCTL[0] register has been received and cleared.
To move to address state, the driver software sets the DEV_ADDR field and the FADDR_EN
flag in the CTRL register.
Once a valid Set Configuration standard request has been received and acknowledged, the
device enables endpoints corresponding to the current configuration. This is done by setting the
BK_NUMBER, EPT_TYPE, EPT_DIR and EPT_SIZE fields in the EPTCFGx registers and
enabling them by setting the EPT_ENABL flag in the EPTCTLENBx registers, and, optionally,
enabling corresponding interrupts in the IEN register.
When a Suspend (no bus activity on the USB bus) is detected, the DET_SUSPD signal in the
INTSTA register is set. This triggers an interrupt if the corresponding bit is set in the IEN register.
This flag is cleared by writing to the CLRINT register. Then the device enters Suspend Mode.
In this state bus powered devices must drain less than 500 µA from the 5V VBUS. As an exam-
ple, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes
into Idle Mode. It may also switch off other devices on the board.
The USBAUSBA device peripheral clocks can be switched off. Resume event is asynchronously
detected.
In Suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver
and clocks disabled (however the pull-up should not be removed).
optionally, enabling the interrupt for endpoint 0 by writing 1 in EPT_INT_0 of the IEN register.
The enumeration then begins by a control transfer.
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