LPC1769FBD100,551 NXP Semiconductors, LPC1769FBD100,551 Datasheet - Page 477
LPC1769FBD100,551
Manufacturer Part Number
LPC1769FBD100,551
Description
IC ARM CORTEX MCU 512K 100-LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheets
1.OM11043.pdf
(79 pages)
2.LPC1767FBD100551.pdf
(2 pages)
3.LPC1767FBD100551.pdf
(840 pages)
4.LPC1769FBD100551.pdf
(66 pages)
Specifications of LPC1769FBD100,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-LQFP
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, Ethernet, I²C, IrDA, Microwire, SPI, SSI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
70
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC17
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
64 KB
Interface Type
Ethernet, USB, OTG, CAN
Maximum Clock Frequency
120 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB1760, MCB1760U, MCB1760UME
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4966
935290522551
935290522551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1769FBD100,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
Table 405: Digital Audio Output register (I2SDAO - address 0x400A 8000) bit description
Table 406: Digital Audio Input register (I2SDAI - address 0x400A 8004) bit description
Table 407: Transmit FIFO register (I2STXFIFO - address 0x400A 8008) bit description
UM10360
User manual
Bit
2
3
4
5
14:6
15
31:16 -
Bit
1:0
2
3
4
5
14:6
31:15 -
Bit
31:0
Symbol
mono
stop
reset
ws_sel
ws_halfperiod
mute
Symbol
I2STXFIFO
Symbol
wordwidth
mono
stop
reset
ws_sel
ws_halfperiod
20.5.2 Digital Audio Input register (I2SDAI - 0x400A 8004)
20.5.3 Transmit FIFO register (I2STXFIFO - 0x400A 8008)
20.5.4 Receive FIFO register (I2SRXFIFO - 0x400A 800C)
Description
8
Value Description
Value Description
×
The I2SDAI register controls the operation of the I
in DAI are shown in
The I2STXFIFO register provides access to the transmit FIFO. The function of bits in
I2STXFIFO are shown in
The I2SRXFIFO register provides access to the receive FIFO. The function of bits in
I2SRXFIFO are shown in
00
01
10
11
32-bit transmit FIFO.
When 1, data is of monaural format. When 0, the data is in stereo format.
When 1, disables accesses on FIFOs, places the transmit channel in mute mode.
When 1, asynchronously resets the transmit channel and FIFO.
When 0, the interface is in master mode. When 1, the interface is in slave mode. See
Section 20.7
Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.
When 1, the transmit channel sends only zeroes.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
Selects the number of bytes in data as follows:
8-bit data
16-bit data
Reserved, do not use this setting
32-bit data
When 1, data is of monaural format. When 0, the data is in stereo format.
When 1, disables accesses on FIFOs, places the transmit channel in mute mode.
When 1, asynchronously reset the transmit channel and FIFO.
When 0, the interface is in master mode. When 1, the interface is in slave mode. See
Section 20.7
Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.
Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
All information provided in this document is subject to legal disclaimers.
for a summary of useful combinations for this bit with I2STXMODE.
for a summary of useful combinations for this bit with I2SRXMODE.
Table
Rev. 2 — 19 August 2010
Table
Table
406.
407.
408.
2
S receive channel. The function of bits
Chapter 20: LPC17xx I2S
UM10360
© NXP B.V. 2010. All rights reserved.
Reset Value
Level = 0
477 of 840
0
0
0
0x1F
0
0
Reset
Value
1
1
NA
Reset
Value
01
0
1
0x1F
NA
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