ADUC841BSZ62-5 Analog Devices Inc, ADUC841BSZ62-5 Datasheet - Page 82
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ADUC841BSZ62-5
Manufacturer Part Number
ADUC841BSZ62-5
Description
IC ADC/DAC 12BIT W/MCU 52-MQFP
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC8xxr
Datasheet
1.EVAL-ADUC842QS.pdf
(88 pages)
Specifications of ADUC841BSZ62-5
Core Size
8-Bit
Program Memory Size
62KB (62K x 8)
Core Processor
8052
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
DMA, PSM, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Type
FLASH
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
4.75 V ~ 5.25 V
Data Converters
A/D 8x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-MQFP, 52-PQFP
Controller Family/series
(8051) 8052
No. Of I/o's
32
Ram Memory Size
2.25KB
Cpu Speed
20MIPS
No. Of Timers
3
No. Of Pwm Channels
2
Embedded Interface Type
UART
Rohs Compliant
Yes
Cpu Family
ADuC8xx
Device Core
8052
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SPI/UART
Total Internal Ram Size
2.25KB
# I/os (max)
34
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
On-chip Adc
8-chx12-bit
On-chip Dac
2-chx12-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
52
Package Type
MQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADUC841QSZ - KIT DEV FOR ADUC841 QUICK START
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADUC841BSZ62-5
Manufacturer:
Analog Devices Inc
Quantity:
135
Company:
Part Number:
ADUC841BSZ62-5
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADuC841/ADuC842/ADuC843
Parameter
SPI MASTER MODE TIMING (CPHA = 1)
t
t
t
t
t
t
t
t
t
1
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 bits in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid after SCLOCK Edge
Data Input Setup Time before SCLOCK Edge
Data Input Hold Time after SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MOSI
MISO
1
1
t
DAV
t
SH
t
DSU
Figure 91. SPI Master Mode Timing (CPHA = 1)
MSB IN
t
MSB
DHD
t
SL
Rev. 0 | Page 82 of 88
t
DF
t
DR
BITS 6–1
BITS 6–1
t
SR
Min
100
100
t
LSB IN
SF
LSB
Typ
476
476
10
10
10
10
Max
50
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns