LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 233
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Manufacturer
Quantity
Price
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LPC2458FET180,551
Manufacturer:
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UM10237_4
User manual
7.2.12 Transmit Consume Index Register (TxConsumeIndex - 0xFFE0 012C)
7.2.13 Transmit Status Vector 0 Register (TSV0 - 0xFFE0 0158)
The Transmit Consume Index register (TxConsumeIndex) is a Read Only register with an
address of 0xFFE0 012C. Its bit definition is shown in
Table 217. Transmit Consume Index register (TxConsumeIndex - address 0xFFE0 012C) bit
The transmit consume index register defines the descriptor that is going to be transmitted
next by the hardware transmit process. After a frame has been transmitted hardware
increments the index, wrapping the value to 0 once the value of TxDescriptorNumber has
been reached. If the TxConsumeIndex equals TxProduceIndex the descriptor array is
empty and the transmit channel will stop transmitting until software produces new
descriptors.
The Transmit Status Vector 0 register (TSV0) is a Read Only register with an address of
0xFFE0 0158. The transmit status vector registers store the most recent transmit status
returned by the MAC. Since the status vector consists of more than 4 bytes, status is
distributed over two registers TSV0 and TSV1. These registers are provided for debug
purposes, because the communication between driver software and the Ethernet block
takes place primarily through the frame descriptors. The status register contents are valid
as long as the internal status of the MAC is valid and should typically only be read when
the transmit and receive processes are halted.
Table 11–218
Table 218. Transmit Status Vector 0 register (TSV0 - address 0xFFE0 0158) bit description
Bit
15:0
31:16
Bit
0
1
2
3
4
5
6
7
8
9
Symbol
TxConsumeIndex Index of the descriptor that is going to be transmitted next by
-
Symbol
CRC error
Length check error
Length out of range
Done
Multicast
Broadcast
Packet Defer
Excessive Defer
Excessive Collision
Late Collision
description
lists the bit definitions of the TSV0 register.
Rev. 04 — 26 August 2009
[1]
Function
the transmit datapath.
Unused
Function
The attached CRC in the packet did not match the
internally generated CRC.
Indicates the frame length field does not match the actual
number of data items and is not a type field.
Indicates that frame type/length field was larger than
1500 bytes.
Transmission of packet was completed.
Packet’s destination was a multicast address.
Packet’s destination was a broadcast address.
Packet was deferred for at least one attempt, but less than
an excessive defer.
Packet was deferred in excess of 6071 nibble times in
100 Mbps or 24287 bit times in 10 Mbps mode.
Packet was aborted due to exceeding of maximum allowed
number of collisions.
Collision occurred beyond collision window, 512 bit times.
Table
Chapter 11: LPC24XX Ethernet
11–217.
UM10237
© NXP B.V. 2009. All rights reserved.
233 of 792
0
Reset
value
0x0
0x0
Reset
value
0
0
0
0
0
0
0
0
0
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