LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 536

• Manufacturer Part Number: LPC2458FET180,551
• Description: IC ARM7 MCU FLASH 512K 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2458FET180,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 136
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 98K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 180-TFBGA
• Processor Series: LPC24
• Core: ARM7TDMI-S
• Data Bus Width: 32 bit
• Data Ram Size: 98 KB
• Interface Type: CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 4
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 10 bit, 1 Channel
• Package: 180TFBGA
• Device Core: ARM7TDMI-S
• Family Name: LPC2000
• Maximum Speed: 72 MHz
• For Use With: 622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4258; 935282454551; LPC2458FET180-S

1. Basic configuration
2. Features
3. Description
UM10237_4
User manual
The SSP0/1 interfaces are configured using the following registers:
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
LPC2400 has two Synchronous Serial Port controllers -- SSP0 and SSP1.
1. Power: In the PCONP register
2. Clock: In PCLK_SEL0 select PCLK_SSP1; in PCLK_SEL1 select PCLK_SSP0 (see
3. Pins: Select SSP pins and their modes in PINSEL0 to PINSEL4 and PINMODE0 to
4. Interrupts: Interrupts are enabled in the SSPnIMSC register
5. Initialization: see
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UM10237
Chapter 20: LPC24XX SSP interface SSP0/1
Rev. 04 — 26 August 2009
Remark: On reset, both SSP interfaces are enabled (PCSSP0/1 = 1).
Section
Section
PINMODE4 (see
are enabled in the VIC using the VICIntEnable register
Remark: In the VIC, the SSP0 shares its interrupts with the SPI interface.
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
Synchronous Serial Communication.
Master or slave operation.
8 frame FIFOs for both transmit and receive.
4 to 16 bits frame.
DMA transfers supported by GPDMA.
4–3.3.4. In master mode, the clock must be scaled down (see
20–6.5).
Table 20–471
Section
Rev. 04 — 26 August 2009
9–5).
(Table
and
Table
4–63), set bit PCSSP0/1.
20–472.
(Table
Table
7–106).
20–476. Interrupts
© NXP B.V. 2009. All rights reserved.
User manual
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