LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 737
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2458FET180,551
Manufacturer:
MICROCHIP
Quantity:
1 103
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Part Number:
LPC2458FET180,551
Manufacturer:
NXP Semiconductors
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UM10237_4
User manual
10.1 Peripheral-to-memory, or Memory-to-peripheral DMA flow
10.2 Peripheral-to-peripheral DMA flow
Table 676. DMA request signal usage
For a peripheral-to-memory or memory-to-peripheral DMA flow the following sequence
occurs:
See
For a peripheral-to-peripheral DMA flow the following sequence occurs:
Transfer Direction
Memory-to-peripheral
Memory-to-peripheral
Peripheral-to-memory
Peripheral-to-memory
Memory-to-memory
Source peripheral to destination
peripheral
Source peripheral to destination
peripheral
Source peripheral to destination
peripheral
1. Program and enable the DMA channel.
2. Wait for a DMA request.
3. The GPDMA starts transferring data when:
4. If an error occurs while transferring the data, an error interrupt is generated and
5. Decrement the transfer count if the GPDMA is performing the flow control.
6. If the transfer has completed (indicated by the transfer count reaching 0 if the GPDMA
1. Program and enable the DMA channel.
2. Wait for a source DMA request.
3. The GPDMA starts transferring data when:
– The DMA request goes active.
– The DMA stream has the highest pending priority.
– The GPDMA is the bus master of the AHB bus.
disables the DMA stream, and the flow sequence ends.
is performing flow control, or by the peripheral sending a DMA request if the
peripheral is performing flow control):
– The GPDMA responds with a DMA acknowledge.
– The terminal count interrupt is generated (this interrupt can be masked).
– If the DMACCxLLI Register is not 0, then reload the DMACCxSrcAddr,
Section 32–4.1
DMACCxDestAddr, DMACCxLLI, and DMACCxControl Registers and go back to
step 2. However, if DMACCxLLI is 0, the DMA stream is disabled and the flow
sequence ends.
Chapter 32: LPC24XX General Purpose DMA (GPDMA) controller
for memory regions accessible by the GPDMA.
Rev. 04 — 26 August 2009
Request Generator
Peripheral
Peripheral
Peripheral
Peripheral
GPDMA
Source peripheral and
destination peripheral
Source peripheral and
destination peripheral
Source peripheral and
destination peripheral
Flow Controller
GPDMA
Peripheral
GPDMA
Peripheral
GPDMA
Source peripheral
Destination peripheral
GPDMA
UM10237
© NXP B.V. 2009. All rights reserved.
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