LPC2458FET180,551 NXP Semiconductors, LPC2458FET180,551 Datasheet - Page 96
LPC2458FET180,551
Manufacturer Part Number
LPC2458FET180,551
Description
IC ARM7 MCU FLASH 512K 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC2400r
Specifications of LPC2458FET180,551
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
136
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
180-TFBGA
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
32 bit
Data Ram Size
98 KB
Interface Type
CAN, Ethernet, I2C, I2S, IrDA, SPI, SSP, UART, USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
136
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, SAB-TFBGA180
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
Package
180TFBGA
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
For Use With
622-1023 - BOARD SCKT ADAPTER FOR TFBGA180622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
568-4258
935282454551
LPC2458FET180-S
935282454551
LPC2458FET180-S
Available stocks
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Quantity
Price
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LPC2458FET180,551
Manufacturer:
MICROCHIP
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1 103
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NXP Semiconductors
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11. External memory interface
UM10237_4
User manual
10.27 Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3 -
Table 94.
0xFFE0 8218, 238, 258, 278)
The EMCStaticWaitTurn0-3 registers enable you to program the number of bus
turnaround cycles. It is recommended that these registers are modified during system
initialization, or when there are no current or outstanding transactions. This can be
ensured by waiting until the EMC is idle, and then entering low-power, or disabled mode.
These registers are accessed with one wait state.
Table 5–95
Table 95.
To prevent bus contention on the external memory data bus, the WAITTURN field controls
the number of bus turnaround cycles added between static memory read and write
accesses. The WAITTURN field also controls the number of turnaround cycles between
static memory and dynamic memory accesses.
External memory interfacing depends on the bank width (32, 16 or 8 bit selected via MW
bits in corresponding EMCStaticConfig register).
If a memory bank is configured to be 32 bits wide, address lines A0 and A1 can be used
as non-address lines. If a memory bank is configured to 16 bits wide, A0 is not required.
However, 8 bit wide memory banks do require all address lines down to A0. Configuring
A1 and/or A0 line(s) to provide address or non-address function is accomplished using the
Pin Function Select Register (see
Bit
4:0
31:5
Bit
3:0
31:4
Symbol
Write wait states
(WAITWR)
-
Symbol
Bus turnaround
cycles
(WAITTURN)
-
Static Memory Write Delay registers0-3 (EMCStaticWaitWr - address 0xFFE0 8214,
0xFFE0 8234, 0xFFE0 8254, 0xFFE0 8274) bit description
Static Memory Trun Round Delay registers0-3 (EMCStaticWaitTurn0-3 - address
0xFFE0 8218, 0xFFE0 8238, 0xFFE0 8258, 0xFFE0 8278) bit description
shows the bit assignments for the EMCStaticWaitTurn0-3 registers.
Rev. 04 — 26 August 2009
Value Description
0x0 -
0x1E
0x1F
-
0x0 -
0xE
0xF
Value Description
-
Chapter 5: LPC24XX External Memory Controller (EMC)
SRAM wait state time for write accesses after the first
read:
(n + 2) CCLK cycle write access time. The wait state time
for write accesses after the first read is WAITWR (n + 2) x
tCCLK.
33 CCLK cycle write access time (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
(n + 1) CCLK turnaround cycles. Bus turnaround time is
(WAITTURN + 1) x tCCLK.
16 CCLK turnaround cycles (POR reset value).
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Section
9–3).
UM10237
© NXP B.V. 2009. All rights reserved.
96 of 792
Reset
Value
0x1F
NA
Reset
Value
0xF
NA
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