LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 276
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
- Current page: 276 of 792
- Download datasheet (5Mb)
NXP Semiconductors
UM10237_4
User manual
9.21 Reset
The Ethernet block has a hard reset input which is connected to the chip reset, as well as
several soft resets which can be activated by setting the appropriate bit(s) in registers. All
registers in the Ethernet block have a value of 0 after a hard reset, unless otherwise
specified.
Hard reset
After a hard reset, all registers will be set to their default value.
Soft reset
Parts of the Ethernet block can be soft reset by setting bits in the Command register and
the MAC1 configuration register.The MAC1 register has six different reset bits:
The above reset bits must be cleared by software.
The Command register has three different reset bits:
•
•
•
•
•
•
•
•
SOFT RESET: Setting this bit will put all modules in the MAC in reset, except for the
MAC registers (at addresses 0x000 to 0x0FC). The value of the soft reset after a
hardware reset assertion is 1, i.e. the soft reset needs to be cleared after a hardware
reset.
SIMULATION RESET: Resets the random number generator in the Transmit Function.
The value after a hardware reset assertion is 0.
RESET MCS/Rx: Setting this bit will reset the MAC Control Sublayer (pause frame
logic) and the receive function in the MAC. The value after a hardware reset assertion
is 0.
RESET Rx: Setting this bit will reset the receive function in the MAC. The value after a
hardware reset assertion is 0.
RESET MCS/Tx: Setting this bit will reset the MAC Control Sublayer (pause frame
logic) and the transmit function in the MAC. The value after a hardware reset
assertion is 0.
RESET Tx: Setting this bit will reset the transmit function of the MAC. The value after
a hardware reset assertion is 0.
TxReset: Writing a ‘1’ to the TxReset bit will reset the transmit datapath, excluding the
MAC portions, including all (read-only) registers in the transmit datapath, as well as
the TxProduceIndex register in the host registers module. A soft reset of the transmit
datapath will abort all AHB transactions of the transmit datapath. The reset bit will be
cleared autonomously by the Ethernet block. A soft reset of the Tx datapath will clear
the TxStatus bit in the Status register.
RxReset: Writing a ‘1’ to the RxReset bit will reset the receive datapath, excluding the
MAC portions, including all (read-only) registers in the receive datapath, as well as the
RxConsumeIndex register in the host registers module. A soft reset of the receive
datapath will abort all AHB transactions of the receive datapath. The reset bit will be
cleared autonomously by the Ethernet block. A soft reset of the Rx datapath will clear
the RxStatus bit in the Status register.
Rev. 04 — 26 August 2009
Chapter 11: LPC24XX Ethernet
UM10237
© NXP B.V. 2009. All rights reserved.
276 of 792
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