LPC2478FBD208,551 NXP Semiconductors, LPC2478FBD208,551 Datasheet - Page 428
LPC2478FBD208,551
Manufacturer Part Number
LPC2478FBD208,551
Description
IC ARM7 MCU 512K LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(91 pages)
2.OM11077.pdf
(792 pages)
3.OM11077.pdf
(10 pages)
4.LPC2478FBD208551.pdf
(89 pages)
Specifications of LPC2478FBD208,551
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/IrDA/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, DK-35TS-LPC2478, DK-57TS-LPC2478, DK-57VTS-LPC2478, SOMDIMM-LPC2478, SAB-TFBGA208, KSK-LPC2478-JL, MCB2470
Development Tools By Supplier
OM11015, OM11019, OM11022
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1034 - PROGRAMMERS, DEVELOPMENT SYSTEMS622-1033 - KIT LCD TOUCH 5.7" FOR LPC2478MCB2470 - BOARD EVAL NXP LPC247X SERIESOM11022 - EVAL LPC-STICK WITH LPC2478OM11019 - BOARD EVAL FOR LPC2478568-4742 - MODULE DIMM LPC2478 ARM7568-4741 - KIT LCD TOUCH 5.7" FOR LPC2478622-1028 - KIT LCD TOUCH 5.7" FOR LPC2478KSDKLPC2478-PL - KIT IAR KICKSTART NXP LPC2478622-1024 - BOARD SCKT ADAPTER FOR TFBGA208568-4369 - BOARD EVAL FOR LPC2478622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4363
935284069551
LPC2478FBD208-S
935284069551
LPC2478FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
LPC2478FBD208,551
Manufacturer:
NXP/恩智浦
Quantity:
20 000
- OM11077 PDF datasheet
- OM11077 PDF datasheet #2
- OM11077 PDF datasheet #3
- LPC2478FBD208551 PDF datasheet #4
- Current page: 428 of 792
- Download datasheet (5Mb)
NXP Semiconductors
UM10237_4
User manual
4.4 UARTn Interrupt Enable Register (U0IER - 0xE000 C004, U2IER -
higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by
zero is not allowed. The Divisor Latch Access Bit (DLAB) in UnLCR must be one in order
to access the UARTn Divisor Latches.
Table 380. UARTn Divisor Latch LSB Register (U0DLL - address 0xE000 C000,
Table 381. UARTn Divisor Latch MSB Register (U0DLM - address 0xE000 C004,
0xE007 8004, U3IER - 0xE007 C004 when DLAB = 0)
The UnIER is used to enable the three UARTn interrupt sources.
Table 382. UARTn Interrupt Enable Register (U0IER - address 0xE000 C004,
Bit
7:0
Bit
7:0
Bit
0
1
2
7:3
8
9
31:10 -
Symbol
DLLSB
Symbol
DLMSB
Symbol
RBR
Interrupt
Enable
THRE
Interrupt
Enable
RX Line
Status
Interrupt
Enable
-
ABEOIntEn
ABTOIntEn
U2DLL - 0xE007 8000, U3DLL - 0xE007 C000 when DLAB = 1) bit description
U2DLM - 0xE007 8004, U3DLM - 0xE007 C004 when DLAB = 1) bit description
U2IER - 0xE007 8004, U3IER - 0xE007 C004 when DLAB = 0) bit description
Description
The UARTn Divisor Latch LSB Register, along with the UnDLM
register, determines the baud rate of the UARTn.
Description
The UARTn Divisor Latch MSB Register, along with the U0DLL
register, determines the baud rate of the UARTn.
Value Description
0
1
0
1
0
1
0
1
0
1
Rev. 04 — 26 August 2009
enables the Receive Data Available interrupt for UARTn. It
also controls the Character Receive Time-out interrupt.
Disable the RDA interrupts.
Enable the RDA interrupts.
enables the THRE interrupt for UARTn. The status of this
can be read from UnLSR[5].
Disable the THRE interrupts.
Enable the THRE interrupts.
enables the UARTn RX line status interrupts. The status of
this interrupt can be read from UnLSR[4:1].
Disable the RX line status interrupts.
Enable the RX line status interrupts.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
enables the end of auto-baud interrupt.
Disable End of Auto-baud Interrupt.
Enable End of Auto-baud Interrupt.
enables the auto-baud time-out interrupt.
Disable Auto-baud Time-out Interrupt.
Enable Auto-baud Time-out Interrupt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 16: LPC24XX UART0/2/3
UM10237
© NXP B.V. 2009. All rights reserved.
Reset Value
0x01
Reset Value
0x00
Reset
Value
0
0
0
NA
0
0
NA
428 of 792
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