EP9307-CRZ Cirrus Logic Inc, EP9307-CRZ Datasheet - Page 371
EP9307-CRZ
Manufacturer Part Number
EP9307-CRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EP9307-CRZ.pdf
(16 pages)
2.EP9307-CRZ.pdf
(50 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9307-CRZ.pdf
(48 pages)
Specifications of EP9307-CRZ
Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
4
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1138
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-CRZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
EP9307-CRZ/E2
Manufacturer:
CIRRUS
Quantity:
20 000
Company:
Part Number:
EP9307-CRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EP9307-CRZ PDF datasheet
- EP9307-CRZ PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9307-CRZ PDF datasheet #4
- Current page: 371 of 824
- Download datasheet (13Mb)
DS785UM1
TxEn:
EH2:
EH1:
EEOB:
RxChR:
RxDis:
Copyright 2007 Cirrus Logic
Transmit Enable. Writing a one to Transmit Enable causes
transmit DMA transfers to be enabled. This is reflected in
TxAct (Bus Master Status) being set. TxEn is an act-once-
bit and will clear automatically when the enable is
complete. The first time the TxEn bit is set following an
AHB reset, or a TxChRes, the MAC performs a transmit
channel initialization. During this initialization the TXDEnq
is cleared, and the Transmit Descriptor and Status Queues
are calculated. When the initialization is complete, the
TxAct (BMSts) is set.
Enable Header 2. When Enable Header2 is set, a status is
written to the receive status queue when the number of
bytes specified in Receive Header Length2 have been
transferred to the receive data buffer. If the transfer either
fills a receive buffer or ends a receive frame, only an end
of buffer or end of frame status is generated. The value in
Receive Header Length 2 should be greater than the value
in Receive Header Length 1 in order to generate a status
event.
Enable Header 1. When Enable Header1 is set, a status is
written to the receive status queue when the number of
bytes specified in Receive Header Length1 have been
transferred to the receive data buffer. If the transfer either
fills a receive buffer or ends a receive frame, only an end
of buffer or end of frame status is generated.
Enable EOB. When Enable End Of Buffer bit is set, a
status is written to the receive status queue whenever an
end of receive buffer is reached. If reaching the end of the
receive buffer coincides with the end of frame, only one
status is written to the queue.
Receive Channel Reset. Writing a “1” to Receive Channel
Reset causes the Receive Descriptor Processor and the
receive FIFO to be reset. This bit is an act-once-bit and
will clear automatically when the reset is complete.
Receive Disable. Writing a “1” to Receive Disable causes
receive DMA transfers to be halted. If a receive frame is
currently in progress, transfers will be halted when the
receive frame status has been transferred to the status
buffer. When the transfers are halted, the RxAct bit (Bus
Master Status) is cleared. This bit is an act-once-bit and
will clear immediately.
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9-69
9
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