EZ80F91AZA50SG Zilog, EZ80F91AZA50SG Datasheet - Page 126
EZ80F91AZA50SG
Manufacturer Part Number
EZ80F91AZA50SG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4564
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS027001-0707
Table 48. Watchdog Timer Control Register
Bit
Reset
CPU Access
Note: R = Read only; R/W = Read/Write.
Bit
Position
7
WDT_EN
6
NMI_OUT
5
RST_FLAG
4
NMI_FLAG
[3:2]
WDT_CLK
Value Description
0
1
0
1
0
1
0
1
00
01
10
11
WDT is disabled.
WDT is enabled. When enabled, the WDT cannot be disabled
without a RESET.
WDT time-out resets the CPU.
WDT time-out generates a NMI to the CPU.
RESET caused by external full-chip reset or ZDI reset.
RESET caused by WDT time-out. This flag is set by the WDT
time-out, only if the NMI_OUT flag is set to 0. The CPU polls
this bit to determine the source of the RESET. This flag is
cleared by a non-WDT generated reset.
NMI caused by external source.
NMI caused by WDT time-out. This flag is set by the WDT time-
out, only if the NMI_OUT flag is set to 1. The CPU polls this bit
to determine the source of the NMI. This flag is cleared by a
non-WDT NMI.
WDT clock source is system clock.
WDT clock source is Real-Time Clock source (32 kHz on-chip
oscillator or 50/60 Hz input as set by RTC_CTRL[4]).
WDT clock source is internal RC oscillator (10 kHz typical).
Reserved
R/W
7
0
R/W
6
0
0/1
R
5
(WDT_CTL = 0093h)
R
4
0
R/W
3
1
Product Specification
R/W
2
0
eZ80F91 ASSP
Watchdog Timer
R/W
1
0
R/W
0
0
118
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