EZ80F91AZA50SG Zilog, EZ80F91AZA50SG Datasheet - Page 332
EZ80F91AZA50SG
Manufacturer Part Number
EZ80F91AZA50SG
Description
IC ACCLAIM MCU 256KB 144LQFP
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91AZA50SG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG
Minimum Operating Temperature
0 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4564
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 209. EMAC Boundary Pointer Register—Upper Byte
Table 210. EMAC Receive High Boundary Pointer Register—Low Byte (EMAC_RHBP_L = 0047h)
PS027001-0707
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
[7:0]
EMAC_BP_U
Bit
Reset
CPU Access
Note: R = Read Only, R/W = Read/Write
Bit
Position
[7:0]
EMAC_RHBP_L
EMAC Receive High Boundary Pointer Register—Low and High Bytes
The Receive High Boundary Pointer Register must be set to the end of the Receive buffer
+1 in EMAC shared memory. This RHBP uses the same RAM_ADDR_U as the
EMAC_BP_U pointer above. See
Value
00h–FFh These bits represent the upper byte of the 3 byte EMAC
Value
00h–E0h These bits represent the Low byte of the 2 byte EMAC
R/W
Description
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 23 of the 24 bit value. Bit 0 is bit 16 of
the 24 bit value.
R
7
1
7
0
Description
Receive High Boundary Pointer value, {EMAC_RHBP_H,
EMAC_RHBP_L}. Bit 7 is bit 7 of the 16 bit value. Bit 0 is bit
0 (lsb) of the 16 bit value.
R/W
R
6
1
6
0
R/W
R
5
1
5
0
Table 210
R
R
4
1
4
0
R
R
3
1
3
0
and
Table 211
R
R
(EMAC_BP_U = 0046h)
2
1
2
0
on page 325.
Ethernet Media Access Controller
R
R
1
1
1
0
Product Specification
R
R
0
1
0
0
eZ80F91 ASSP
324
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