EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 243
EZ80F91NAA50EG
Manufacturer Part Number
EZ80F91NAA50EG
Description
IC ACCLAIM MCU 256KB 144BGA
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91NAA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG, eZ80F910200KITG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4565
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Zilog Debug Interface
PS027001-0707
Introduction
The Zilog Debug Interface (ZDI) provides a built-in debugging interface to the CPU. ZDI
provides basic in-circuit emulation features including:
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•
•
•
•
•
•
•
•
The above features are built into the silicon. Control is provided via a two-wire interface
that is connected to the ZPAK II emulator.
target board, ZPAK II, and the host PC running Zilog Developer Studio II. For more infor-
mation on ZPAK II and ZDS II, refer to www.zilog.com.
ZDI allows reading and writing of most internal registers without disturbing the state of
the machine. Reads and Writes to memory occurs as fast as the ZDI downloads and
Developer
Examining and modifying internal registers.
Examining and modifying memory.
Starting and stopping the user program.
Setting program and data break points.
Single-stepping the user program.
Executing user-supplied instructions.
Debugging the final product with the inclusion of one small connector.
Downloading code into SRAM.
C source-level debugging using Zilog Developer Studio II (ZDS II).
ZiLOG
Studio
Figure 48. Typical ZDI Debug Setup
Emulator
ZPAK
Figure 48
illustrates a typical setup using a a
O
O
C
N
N
E
C
R
T
Target Board
Product Specification
Product
eZ80
Zilog Debug Interface
eZ80F91 ASSP
235
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