EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 304
EZ80F91NAA50EG
Manufacturer Part Number
EZ80F91NAA50EG
Description
IC ACCLAIM MCU 256KB 144BGA
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91NAA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG, eZ80F910200KITG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4565
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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PS027001-0707
Table 176. EMAC Interrupts
Interrupt
EMAC System Interrupts
EMAC Transmitter Interrupts
EMAC Receiver Interrupts
Transmit State Machine Error
MIIMGT Done
Receive Overrun
Transmit Control Frame
Transmit Done
Receive Packet
Receive Pause Packet
Receive Done
EMAC Interrupts
EMAC Shared Memory Organization
Eight different sources of interrupts from the EMAC are described in
Internal Ethernet SRAM shares memory with the CPU. This memory is divided into the
Transmit buffer and the Receive buffer by defining three registers, as listed below.
•
•
Transmit Lower Boundary Pointer (TLBP)—this register points to the start of the
Transmit buffer in the internal Ethernet shared memory space.
Boundary Pointer (BP)—this register points to the start of the Receive buffer.
Description
Bit 7 (TxFSMERR_STAT) of the EMAC Interrupt Status Register
(EMAC_ISTAT). A Transmit State Machine Error must not occur.
However, if this bit is set, the entire transmitter module must be
reset.
Bit 6 (MGTDONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). This bit is set when communicating to the PHY
over the MII during a Read or Write operation.
Bit 2 (Rx_OVR_STAT) of the Interrupt Status Register
(EMAC_ISTAT). If this bit is set, all incoming packets are ignored
until this bit is cleared by software.
Transmit Control Frame = Bit 1 (Tx_CF_STAT) of the Interrupt
Status Register (EMAC_ISTAT). Denotes when control frame
transmission is complete.
Bit 0 (Tx_DONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet transmission is complete.
Bit 5 (Rx_CF_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet reception is complete.
Bit 4 (Rx_PCF_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when pause packet reception is
complete.
Bit 3 (Rx_DONE_STAT) of the Interrupt Status Register
(EMAC_ISTAT). Denotes when packet reception is complete.
Ethernet Media Access Controller
Product Specification
Table
eZ80F91 ASSP
176.
296
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