EZ80F91NAA50EG Zilog, EZ80F91NAA50EG Datasheet - Page 97
EZ80F91NAA50EG
Manufacturer Part Number
EZ80F91NAA50EG
Description
IC ACCLAIM MCU 256KB 144BGA
Manufacturer
Zilog
Series
eZ80® AcclaimPlus!™r
Datasheet
1.EZ80F91AZA50SG.pdf
(387 pages)
Specifications of EZ80F91NAA50EG
Core Processor
Z8
Core Size
8-Bit
Speed
50MHz
Connectivity
Ethernet, I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
144-LBGA
Processor Series
EZ80F91x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F910300ZCOG, eZ80F910200KITG
Minimum Operating Temperature
- 40 C
For Use With
269-4712 - KIT DEV ENCORE 32 SERIES269-4671 - BOARD ZDOTS SBC Z80ACCLAIM PLUS269-4561 - KIT DEV FOR EZ80F91 W/C-COMPILER269-4560 - KIT DEV FOR EZ80F91 W/C-COMPILER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-4565
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (5Mb)
PS027001-0707
Bit
Position
[3:0]
BUS_CYCLE
Notes
1. Setting the BUS_CYCLE to 1 in Intel bus mode causes the ALE pin to not function properly.
2. Use of the external WAIT input pin in Z80 mode requires that BUS_CYCLE is set to a value
3. BUS_CYCLE produces no effect in eZ80 mode.
greater than 1.
Bus Arbiter
The Bus Arbiter within the eZ80F91 allows external bus masters to gain control of the
CPU memory interface bus. During normal operation, the eZ80F91 device is the bus mas-
ter. External devices request master use of the bus by asserting the BUSREQ pin. The Bus
Arbiter forces the CPU to release the bus after completing the current instruction. When
the CPU releases the bus, the Bus Arbiter asserts the BUSACK pin to notify the external
device that it can master the bus. When an external device assumes control of the memory
interface bus, the bus acknowledge cycle is complete.
tus of the pins on the eZ80F91 device during bus acknowledge cycles.
During a bus acknowledge cycle, the bus interface pins of the eZ80F91 device are used by
an external bus master to control the memory and I/O chip selects.
Value Description
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not valid.
Each bus mode state is 1 eZ80 clock cycle in duration.
Each bus mode state is 2 eZ80 clock cycles in duration.
Each bus mode state is 3 eZ80 clock cycles in duration.
Each bus mode state is 4 eZ80 clock cycles in duration.
Each bus mode state is 5 eZ80 clock cycles in duration.
Each bus mode state is 6 eZ80 clock cycles in duration.
Each bus mode state is 7 eZ80 clock cycles in duration.
Each bus mode state is 8 eZ80 clock cycles in duration.
Each bus mode state is 9 eZ80 clock cycles in duration.
Each bus mode state is 10 eZ80 clock cycles in duration.
Each bus mode state is 11 eZ80 clock cycles in duration.
Each bus mode state is 12 eZ80 clock cycles in duration.
Each bus mode state is 13 eZ80 clock cycles in duration.
Each bus mode state is 14 eZ80 clock cycles in duration.
Each bus mode state is 15 eZ80 clock cycles in duration.
Table 31
on page 90 shows the sta-
Chip Selects and Wait States
Product Specification
1, 2, 3
eZ80F91 ASSP
89
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