R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 130
R5F212B7SNFP#U0
Manufacturer Part Number
R5F212B7SNFP#U0
Description
IC R8C/2B MCU FLASH 64-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Br
Specifications of R5F212B7SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
10.5
10.5.1
Table 10.2
−: can be 0 or 1, no change in outcome
High-speed
clock mode
Low-speed
clock mode
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
There are three power control modes. All modes other than wait mode and stop mode are referred to as standard
operating mode.
Standard operating mode is further separated into four modes.
In standard operating mode, the CPU clock and the peripheral function clock are supplied to operate the CPU
and the peripheral function clocks. Power consumption control is enabled by controlling the CPU clock
frequency. The higher the CPU clock frequency, the more processing power increases. The lower the CPU
clock frequency, the more power consumption decreases. When unnecessary oscillator circuits stop, power
consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source needs to be oscillating
and stable. If the new clock source is the XIN clock or XCIN clock, allow sufficient wait time in a program
until oscillation is stabilized before exiting.
Power Control
Nov 26, 2007
Modes
Standard Operating Mode
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
No division
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
Settings and Modes of Clock Associated Bits
Page 108 of 580
Register
OCD2
OCD
0
0
0
0
0
−
1
1
1
1
1
1
1
1
1
1
CM17,
CM16
00b
01b
10b
00b
01b
10b
00b
01b
10b
11b
11b
11b
−
−
−
−
CM1 Register
CM14
−
−
−
−
−
−
−
−
−
−
−
0
0
0
0
0
CM13
1
1
1
1
1
−
−
−
−
−
−
−
−
−
−
−
CM07
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
CM06
CM0 Register
0
0
0
1
0
−
0
0
0
1
0
0
0
0
1
0
CM05
0
0
0
0
0
−
−
−
−
−
−
−
−
−
−
−
10. Clock Generation Circuit
CM04 FRA01 FRA00
−
−
−
−
−
1
−
−
−
−
−
−
−
−
−
−
FRA0 Register
−
−
−
−
−
−
1
1
1
1
1
0
0
0
0
0
−
−
−
−
−
−
1
1
1
1
1
−
−
−
−
−
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