R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 458
R5F212B7SNFP#U0
Manufacturer Part Number
R5F212B7SNFP#U0
Description
IC R8C/2B MCU FLASH 64-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Br
Specifications of R5F212B7SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 16.34
16.3.3
(1) I
(2) I
Explanation of symbols
S
SLA
R/W
A
DATA : Transmit / receive data
P
16.3.3.1
(a) I
(b) I
2
2
C bus format
C bus timing
Setting the FS bit in the SAR register to 0 enables communication in I
Figure 16.34 shows the I
8 bits.
: Start condition
: Slave address
: Indicates the direction of data transmit/receive
2
2
: Acknowledge
: Stop condition
The master device changes the SDA signal from “H” to “L” while the SCL signal is held “H”.
Data is transmitted from the slave device to the master device when R/W value is 1 and from the master device to the slave device when
The receive device sets the SDA signal to “L”.
The master device changes the SDA signal from “L” to “H” while the SCL signal is held “H”.
C bus format (FS = 0)
C bus format (when start condition is retransmitted, FS = 0)
R/W value is 0.
SDA
SCL
Nov 26, 2007
S
S
1
1
I
2
C bus Interface Mode
S
I
I
2
2
C bus Format and Bus Timing
C bus Format
SLA
SLA
7
7
1 to 7
SLA
1
1
Page 436 of 580
R/W
R/W
8
1
R/W
1
2
C bus Format and Bus Timing. The 1st frame following the start condition consists of
A
A
1
1
9
A
DATA
DATA
n
n1
1 to 7
m1
DATA
8
A
1
m
A/A
1
9
A
S
1
A/A
1 to 7
1
SLA
7
P
1
DATA
1
2
8
Transfer bit count (n = 1 to 8)
Transfer frame count (m = from 1)
16. Clock Synchronous Serial Interface
C bus format.
R/W
1
9
A
Upper: Transfer bit count (n1, n2 = 1 to 8)
Lower: Transfer frame count (m1, m2 = 1 or more)
A
1
P
DATA
n2
m2
A/A
1
P
1
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