R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 471
R5F212B7SNFP#U0
Manufacturer Part Number
R5F212B7SNFP#U0
Description
IC R8C/2B MCU FLASH 64-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Br
Specifications of R5F212B7SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
Figure 16.45
16.3.4.3
ICDRR register
ICDRS register
ICCR1 register
ICCR1 register
ICSR register
In receive mode, data is latched at the rising edge of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to 1 and input when the MST bit is set to 0.
Figure 16.45 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are as follows.
by program
Processing
RDRF bit in
MST bit in
TRS bit in
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set bits CKS0 to CKS3 in the
(2) The output of the receive clock starts when the MST bit is set to 1 while the transfer clock is being
(3) Data is transferred from registers ICDRS to ICDRR and the RDRF bit in the ICSR register is set to 1,
(4) When the MST bit is set to 1, set the RCVD bit in the ICCR1 register to 1 (disables the next receive
Nov 26, 2007
(input)
SDA
SCL
ICCR1 register and set the MST bit (initial setting).
output.
when the receive operation is completed. Since the next byte of data is enabled when the MST bit is set
to 1, the clock is output continuously. Continuous reception is enabled by reading the ICDRR register
every time the RDRF bit is set to 1. An overrun is detected at the rise of the 8th clock cycle while the
RDRF bit is set to 1, and the AL bit in the ICSR register is set to 1. At this time, the last receive data is
retained in the ICDRR register.
operation) and read the ICDRR register. The SCL signal is fixed “H” after reception of the following
byte of data is completed.
Receive Operation
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
1
0
1
0
1
0
(2) Set MST bit to 1
(when transfer clock is output)
Page 449 of 580
b0
1
b1
Data 1
2
(3) Read ICDRR register
b6
7
b7
8
b0
Data 1
1
16. Clock Synchronous Serial Interface
Data 2
b6
7
(3) Read ICDRR register
b7
8
Data 2
1
b0
Data 3
2
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