R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 508
R5F212B7SNFP#U0
Manufacturer Part Number
R5F212B7SNFP#U0
Description
IC R8C/2B MCU FLASH 64-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Br
Specifications of R5F212B7SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
18.7
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Write to each bit (other than ADST bit) in the ADCON0 register, each bit in the ADCON1 register, or the SMP
bit in the ADCON2 register when A/D conversion is stopped (before a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for at least 1 µs before starting the A/D conversion.
After changing the A/D operating mode, select an analog input pin again.
When using the one-shot mode, ensure that A/D conversion is completed before reading the AD0 register. The
IR bit in the ADIC register or the ADST bit in the ADCON0 register can be used to determine whether A/D
conversion is completed.
When using the repeat mode 0, select the frequency of the A/D converter operating clock φAD or more for the
CPU clock during A/D conversion.
Do not select the fOCO-F for the φAD.
If the ADST bit in the ADCON0 register is set to 0 (A/D conversion stops) by a program and A/D conversion
is forcibly terminated during an A/D conversion operation, the conversion result of the A/D converter will be
undefined. If the ADST bit is set to 0 by a program, do not use the value of the AD0 register.
Connect 0.1 µF capacitor between the VREF pin and AVSS pin.
Do not enter stop mode during A/D conversion.
Do not enter wait mode when the CM02 bit in the CM0 register is set to 1 (peripheral function clock stops in
wait mode) during A/D conversion.
Notes on A/D Converter
Nov 26, 2007
Page 486 of 580
18. A/D Converter
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