R5F212B7SNFP#U0 Renesas Electronics America, R5F212B7SNFP#U0 Datasheet - Page 568
R5F212B7SNFP#U0
Manufacturer Part Number
R5F212B7SNFP#U0
Description
IC R8C/2B MCU FLASH 64-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/2Br
Specifications of R5F212B7SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K5212D8S001BE - KIT STARTER FOR R8C/2DR0K5212D8S000BE - KIT DEV FOR R8C/2D
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/2A Group, R8C/2B Group
Rev.2.00
REJ09B0324-0200
22.2
22.2.1
22.2.2
22.2.3
Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU reads
interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt sequence. At
this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an unexpected interrupt to be
generated.
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting a value in the SP, the program may run out of control.
Either “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal input
to pins INT0 to INT3 and pins KI0 to KI3, regardless of the CPU clock.
For details, refer to Table 21.22 (VCC = 5V), Table 21.29 (VCC = 3V), Table 21.36 (VCC = 2.2V) External
Interrupt INTi (i = 0, 2, 3) Input and Table 21.19 (VCC = 5V), Table 21.26 (VCC = 3V), Table 21.33 (VCC
= 2.2V) TRAIO Input, INT1 Input.
Notes on Interrupts
Nov 26, 2007
Reading Address 00000h
SP Setting
External Interrupt and Key Input Interrupt
Page 546 of 580
22. Usage Notes
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