R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 358
R5F21256SNFP#U0
Manufacturer Part Number
R5F21256SNFP#U0
Description
IC R8C MCU FLASH 32K 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21256SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21256SNFP#U0R5F21256SNFP#ES
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 16.25
IIC bus Control Register 2
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously.
Do not w rite during a transfer operation.
This bit is enabled in master mode. When w riting to the BBSY bit, w rite 0 to the SCP bit using the MOV
instruction simultaneously. Execute the same w ay w hen the start condition is regenerating.
This bit is disabled w hen the clock synchronous serial format is used.
Feb 29, 2008
b3 b2 b1
ICCR2 Register
b0
Bit Symbol
SDAOP
Symbol
IICRST
SDAO
ICCR2
SCLO
BBSY
(b0)
(b2)
SCP
Page 339 of 485
—
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
IIC control part reset bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
SCL monitor flag
SDAO w rite protect bit
SDA output value control
bit
Start/stop condition
generation disable bit
Bus busy bit
Address
Bit Name
00B9h
(4)
When hang-up occurs due to communication failure
during I
control block of the I
ports or initializing registers.
1 : SCL pin is set to “H”
When read, the content is 1.
When read
0 : SDA pin output is held “L”
1 : SDA pin output is held “H”
When w ritten
0 : SDA pin output is changed to “L”
1 : SDA pin output is changed to high-impedance
When w riting to the to BBSY bit, w rite 0
simultaneously.
When read, the content is 1.
Writing 1 is invalid.
When read
0 : Bus is in released state
1 : Bus is in occupied state
When w ritten
0 : Generates stop condition
1 : Generates start condition
0 : SCL pin is set to “L”
When rew rite to SDAO bit, w rite 0 simultaneously.
(“H” output via external pull-up resistor)
(SDA signal changes from “L” to “H” w hile SCL
(SDA signal changes from “H” to “L” w hile SCL
signal is in “H” state)
signal is in “H” state)
2
C bus interface operation, w rite 1, to reset the
(1,2)
(3)
(3)
2
16. Clock Synchronous Serial Interface
C bus interface w ithout setting
After Reset
01111101b
Function
(1)
RW
RW
RW
RW
RW
RW
RO
—
—
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