R5F21256SNFP#U0 Renesas Electronics America, R5F21256SNFP#U0 Datasheet - Page 395
R5F21256SNFP#U0
Manufacturer Part Number
R5F21256SNFP#U0
Description
IC R8C MCU FLASH 32K 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21246SDFPU0.pdf
(61 pages)
3.R5F21246SDFPU0.pdf
(527 pages)
Specifications of R5F21256SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21256SNFP#U0R5F21256SNFP#ES
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 17.8
Timer RA Set the pulse width measurement level low
Timer RA Set the count source (f1, f2, f8, fOCO)
Timer RA Set the Synch Break width
Hardware LIN Set the LIN operation to stop
Hardware LIN Set to slave mode
Hardware LIN Set the LIN operation to start
Hardware LIN Set the RXD0 input unmasking timing
Hardware LIN Set the register to enable interrupts
Timer RA Set to pulse width measurement mode
Timer RA Set the INT1/TRAIO pin to P1_5
Feb 29, 2008
Bits TCK0 to TCK2 in the TRAMR register
TRAPRE register
TRA register
TEDGSEL bit in the TRAIOC register ← 0
Bits TMOD0 to TMOD2 in the TRAMR register ← 011b
TIOSEL bit in the TRAIOC register ← 1
LINE bit in the LINCR register ← 1
Example of Header Field Reception Flowchart (1)
(After Synch Break detection, or after Synch
Field measurement)
SBE bit in the LINCR register
(Bus collision detection, Synch Break detection,
Synch Field measurement)
Bits BCIE, SBIE, SFIE in the LINCR register
MST bit in the LINCR register ← 0
LINE bit in the LINCR register ← 0
Page 376 of 485
A
For the hardware LIN
function, set the TIOSEL bit
in the TRAIOC register to 1.
Set the count source and registers
TRA and TRAPRE as appropriate
for the Synch Break period.
Select the timing at which to
unmask the RXD0 input for UART0.
If the RXD0 input is chosen to be
unmasked after detection of Synch
Break, the Synch Field signal is
also input to UART0.
17. Hardware LIN
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