MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 299
MCHC908MR8VFAE
Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MCHC908MR8VFAE.pdf
(372 pages)
Specifications of MCHC908MR8VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MCHC908MR8VFAE
Manufacturer:
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Quantity:
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MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
The external interrupt pins are falling-edge-triggered and are
software-configurable to be both falling-edge and low-level-triggered.
The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ
pin.
When the interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of these occur:
The vector fetch or software clear can occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending.
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
See
•
•
Figure
Vector fetch, software clear, or reset
Return of the interrupt pin to logic 1
16-3.
External Interrupt (IRQ)
External Interrupt (IRQ)
Functional Description
Technical Data
299
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