MCHC908MR8VFAE Freescale Semiconductor, MCHC908MR8VFAE Datasheet - Page 53
MCHC908MR8VFAE
Manufacturer Part Number
MCHC908MR8VFAE
Description
IC MCU 8K FLASH 8MHZ PWM 32-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MCHC908MR8VFAE.pdf
(372 pages)
Specifications of MCHC908MR8VFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-LQFP
Processor Series
HC08MR
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MCHC908MR8VFAE
Manufacturer:
Freescale
Quantity:
8 393
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Manufacturer:
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Technical Data — MC68HC908MR8
3.1 Contents
3.2 Introduction
3.3 Functional Description
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
NOTE:
3.2
3.3
This section describes the 256 bytes of random-access memory (RAM)
on the MC68HC908MR8.
Addresses $0060–$015F are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
For correct operation, the stack pointer must point only to RAM
locations.
Within page zero are 160 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for input/output (I/O) control and user data or code. When the stack
pointer is moved from its reset location at $00FF, direct addressing
mode instructions can access efficiently all page zero RAM locations.
Page zero RAM, therefore, provides ideal locations for frequently
accessed global variables.
Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the central processor unit (CPU) registers.
For M6805 compatibility, the H register is not stacked.
Section 3. Random-Access Memory (RAM)
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Random-Access Memory (RAM)
Technical Data
53
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