D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 1154
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
135
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas
Quantity:
675
Company:
Part Number:
D12321VF25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1122 of 1268
REJ09B0220-0600
Full address mode (cont)
Bit
DMACRB
Initial value
Read/Write
:
:
:
:
Reserved
Only 0 should be
written to this bit
R/W
—
Destination Address Increment/Decrement
7
0
0
1
0
1
0
1
DAID
R/W
6
0
MARB is fixed
MARB is incremented after a data transfer
MARB is fixed
MARB is decremented after a data transfer
DAIDE
R/W
Data Transfer Factor
DTF
5
0
0
1
3
DTF
Reserved
Only 0 should be
written to this bit
0
1
0
1
2
DTF
R/W
0
1
0
1
0
1
0
1
—
1
4
0
DTF
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Activated by A/D converter conversion
end interrupt
Activated by DREQ pin falling edge input
Activated by DREQ pin low-level input
Activated by SCI channel 0 transmission
data-empty interrupt
Activated by SCI channel 0 reception
data-full interrupt
Activated by SCI channel 1 transmission
data-empty interrupt
Activated by SCI channel 1 reception
data-full interrupt
Activated by TPU channel 0 compare
match/input capture A interrupt
Activated by TPU channel 1 compare
match/input capture A interrupt
Activated by TPU channel 2 compare
match/input capture A interrupt
Activated by TPU channel 3 compare
match/input capture A interrupt
Activated by TPU channel 4 compare
match/input capture A interrupt
Activated by TPU channel 5 compare
match/input capture A interrupt
DTF3
—
—
R/W
—
3
0
Block Transfer Mode
DTF2
R/W
2
0
DTF1
R/W
1
0
DTF0
R/W
0
0
Auto-request (cycle
steal)
Activated by DREQ
pin falling edge input
Activated by DREQ
pin low-level input
—
—
—
—
Auto-request (burst)
—
—
—
—
—
—
—
—
Normal Mode
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