D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 187
D12321VF25V
Manufacturer Part Number
D12321VF25V
Description
IC H8S/2300 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.D12322RVF25V.pdf
(1304 pages)
Specifications of D12321VF25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
86
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read cycles are performed in different areas.
Bit 7
ICIS1
0
1
Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted
between bus cycles when successive external read and external write cycles are performed .
Bit 6
ICIS0
0
1
Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface
area.
Bit 5
BRSTRM
0
1
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
0
1
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Description
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
Description
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
Description
Area 0 is basic bus interface area
Area 0 is burst ROM interface area
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
Rev.6.00 Sep. 27, 2007 Page 155 of 1268
Section 6 Bus Controller
REJ09B0220-0600
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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