D12321VF25V Renesas Electronics America, D12321VF25V Datasheet - Page 216

• Manufacturer Part Number: D12321VF25V
• Description: IC H8S/2300 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12321VF25V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Bus Controller
6.5.3
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.6
shows the relation between the settings of MXC1 and MXC0 and the shift size.
Table 6.6
Row
address
Column
address
6.5.4
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, ×16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D
space both the upper and lower halves of the data bus, D
Access sizes and data alignment are the same as for the basic bus interface. For details, see section
6.4.2, Data Size and Data Alignment.
Rev.6.00 Sep. 27, 2007 Page 184 of 1268
REJ09B0220-0600
MXC1 MXC0 Size
0
1
—
Address Multiplexing
Data Bus
MCR
Address Multiplexing Settings by Bits MXC1 and MXC0
—
0
1
0
1
Shift
—
8 bits
9 bits
10 bits
Setting
prohibited
A
A
A
A
A
—
23
23
23
23
23
to A
to A
to A
to A
to A
13
13
13
13
13
A
A
A
A
A
— — — — — — — — — — — — —
12
12
20
12
12
A
A
A
A
A
11
19
20
11
11
A
A
A
A
A
10
10
18
19
20
15
A
A
A
A
A
15
to D
9
9
17
18
19
to D
Address Pins
A
A
A
A
A
8
8
16
17
18
8
, is enabled, while in 16-bit DRAM
0
, are enabled.
A
A
A
A
A
7
7
15
16
17
A
A
A
A
A
6
6
14
15
16
A
A
A
A
A
5
13
14
15
5
A
A
A
A
A
4
4
12
13
14
A
A
A
A
A
3
3
11
12
13
A
A
A
A
A
2
10
11
12
2
A
A
A
A
A
1
1
9
10
11
A
A
A
A
A
0
0
8
9
10