M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 75

• Manufacturer Part Number: M30800SAGP-BL#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP-BL#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Figure 7.11 RD Signal Output Extended by RDY Signal
0
C
1
9
0 .
8 /
B
0
0
0
2
7
G
N
1
o
o r
0 -
. v
(2) Multiplexed Bus with 2 Wait States
(1) Separate Bus with 2 Wait States
u
1
p
0
0
NOTE:
, 1
0
_____
BCLK
RD
CS
(i=0 to 3)
RDY
BCLK
RD
CS
(i=0 to 3)
RDY
1. The chip-select signal (CSi) may be output longer depending on CPU state such as the instruction
2
tsu
Timing to receive RDY for j wait(s): j+1 cycles (j = 1 to 3)
i
i
queue buffer.
0
(1)
(1)
0
(RDY-BCLK)
5
: Wait states inserted by RDY
: Wait states inserted by program
Page 54
1st cycle
1st cycle
: Setup time for RDY input
f o
3
3
0
2nd cycle
2nd cycle
________
Timing to receive RDY
Timing to receive RDY
3rd cycle
3rd cycle
tsu(RDY - BCLK)
tsu(RDY - BCLK)
4th cycle
4th cycle
7. Bus