M30800SAGP-BL#U5 Renesas Electronics America, M30800SAGP-BL#U5 Datasheet - Page 76
![IC M32C/80 MCU ROMLESS 100LQFP](/photos/12/19/121989/m30800sagp-bl_u_sml.jpg)
M30800SAGP-BL#U5
Manufacturer Part Number
M30800SAGP-BL#U5
Description
IC M32C/80 MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheet
1.M30800SAGP-BLU5.pdf
(354 pages)
Specifications of M30800SAGP-BL#U5
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
45
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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Table 7.8 External Bus States when Accessing Internal Space
Figure 7.12 Bus Priority Order
Table 7.7 Microcomputer Status in Hold State
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7.2.8 External Bus Status when Accessing Internal Space
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7.2.7 HOLD Signal
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7.2.9 BCLK Output
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Table 7.8 shows external bus states when an internal space is accessed.
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The HOLD signal transfers bus privileges from the CPU to external circuits. When a low-level ("L") signal is
applied to the HOLD pin, the microcomputer enters a hold state after bus access is completed. While the
__________
HOLD pin is held "L", the microcomputer is in a hold state and the HLDA pin outputs an "L" signal.
Table 7.7 shows the microcomputer status in a hold state.
Bus is used in the following priority order: HOLD, DMAC, CPU.
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The CPU clock operates the CPU. P5
PM0 register is set to "0" (BCLK) and the CM01 and CM00 bits in the CM0 register are set to "00
port P5
No BCLK is output in single-chip mode. Refer to 8. Clock Generation Circuit for details.
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Page 55
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