MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 105

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.4.1.2
The Flash command controller is used to supervise the command write sequence to execute program,
erase, and erase verify algorithms.
Before starting a command write sequence, the ACCERR and PVIOL flags in the FSTAT register must be
clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers.
If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be started.
If the CBEIF flag is clear, indicating the buffers are not available, a new command write sequence will
overwrite the contents of the address, data, and command buffers.
A command write sequence consists of three steps which must be strictly adhered to with writes to the
Flash module not permitted between the steps. However, Flash register and array reads are allowed during
a command write sequence. The basic command write sequence is as follows:
The address written in step 1 will be stored in the FADDR registers and the data will be stored in the
FDATA registers. When the CBEIF flag is cleared in step 3, the CCIF flag is cleared by the Flash command
controller indicating that the command was successfully launched. For all command write sequences, the
CBEIF flag will set after the CCIF flag is cleared indicating that the address, data, and command buffers
are ready for a new command write sequence to begin. A buffered command will wait for the active
operation to be completed before being launched. Once a command is launched, the completion of the
command operation is indicated by the setting of the CCIF flag in the FSTAT register. The CCIF flag will
set upon completion of all active and buffered commands.
Freescale Semiconductor
1. Write to a valid address in the Flash array memory.
2. Write a valid command to the FCMD register.
3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the command.
Command Write Sequence
MC9S12E128 Data Sheet, Rev. 1.07
Chapter 2 128 Kbyte Flash Module (FTS128K1V1)
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