MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 167

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2
This section lists and describes the signals that connect off chip.
4.2.1
These pins provides operating voltage (V
the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required V
and V
4.2.2
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter
to eliminate the VCO input ripple. The value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. Refer to the device overview chapter
for calculation of PLL loop filter (XFC) components. If PLL usage is not required the XFC pin must be
tied to V
Freescale Semiconductor
1
Refer to the device overview section for availability of the low-voltage reset feature.
SSPLL
XCLKS
EXTAL
XTAL
DDPLL
External Signal Description
RESET
V
V
V
XFC — PLL Loop Filter Pin
must be connected properly.
XFC
DDPLL
SSPLL
DDPLL
Regulator
Monitor
Oscil-
.
Voltage
Clock
lator
, V
SSPLL
OSCCLK
PLL
CRG
Power-on Reset
Low Voltage Reset
— PLL Operating Voltage, PLL Ground
PLLCLK
Figure 4-1. CRG Block Diagram
MC9S12E128 Data Sheet, Rev. 1.07
CM fail
DDPLL
) and ground (V
Clock and Reset
1
Clock Quality
COP
Registers
Control
Checker
Generator
Reset
SSPLL
RTI
Chapter 4 Clocks and Reset Generator (CRGV4)
) for the PLL circuitry. This allows
Real-Time Interrupt
PLL Lock Interrupt
Self-Clock Mode
Oscillator Clock
System Reset
Core Clock
Bus Clock
Interrupt
DDPLL
167