MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 226

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2)
6.3.2.12
Read: Anytime
Write: anytime
6.3.2.13
Read: Anytime
Write: Anytime
226
IEN[15:8]
Reset
Reset
IEN[7:0]
Field
Field
7:0
7:0
W
W
R
R
IEN15
IEN7
ATD Input Enable Register 0 (ATDDIEN0)
ATD Input Enable Register 1 (ATDDIEN1)
0
0
7
ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input
pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
7
ATD Digital Input Enable on Channel Bits — This bit controls the digital input buffer from the analog input
pin (ANx) to PTADx data register.
0 Disable digital input buffer to PTADx
1 Enable digital input buffer to PTADx.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
IEN14
IEN6
0
0
6
6
Figure 6-14. ATD Input Enable Register 0 (ATDDIEN0)
Figure 6-15. ATD Input Enable Register 1 (ATDDIEN1)
Table 6-19. ATDDIEN0 Field Descriptions
Table 6-20. ATDDIEN1 Field Descriptions
IEN13
IEN5
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
5
IEN12
IEN4
0
0
4
4
Description
Description
IEN11
IEN3
0
0
3
3
IEN10
IEN2
0
0
2
2
Freescale Semiconductor
IEN9
IEN1
0
0
1
1
IEN8
IEN0
0
0
0
0

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