MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 228

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 6 Analog-to-Digital Converter (ATD10B16CV2)
6.3.2.15
The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs
AN7-0.
Read: Anytime
Write: Anytime, no effect
The A/D input channels may be used for general-purpose digital input.
228
Function
PTAD[7:8]
Reset
Field
Pin
7:0
W
R
PTAD7
AN 7
Port Data Register 1 (PORTAD1)
1
7
A/D Channel x (ANx) Digital Input Bits — If the digital input buffer on the ANx pin is enabled (IENx=1) or
channel x is enabled as external trigger (ETRIGE = 1, ETRIGCH[3-0] = x, ETRIGSEL = 0) read returns the
logic level on ANx pin (signal potentials not meeting V
If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns
a “1”.
Reset sets all PORTAD1 bits to “1”.
= Unimplemented or Reserved
PTAD6
AN6
1
6
Figure 6-17. Port Data Register 1 (PORTAD1)
Table 6-22. PORTAD1 Field Descriptions
PTAD5
AN5
MC9S12E128 Data Sheet, Rev. 1.07
1
5
PTAD4
AN4
1
4
Description
IL
or V
PTAD3
AN3
1
3
IH
specifications will have an indeterminate value)).
PTAD2
AN2
1
2
Freescale Semiconductor
PTAD1
AN1
1
1
PTAD0
AN0
1
0

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