MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 345

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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11.3.2.20 PMF Enable Control A Register (PMFENCA)
Read and write anytime.
Freescale Semiconductor
Module Base + 0x0020
PWMRIEA
PWMENA
LDOKA
Reset
Field
7
1
0
W
R
PWMENA
PWM Generator A Enable — When MTG is clear, this bit when set enables the PWM generators A, B and C
and the PWM0–5 pins. When PWMENA is clear, PWM generators A, B and C are disabled, and the PWM0–5
pins are in their inactive states unless the corresponding OUTCTLx bits are set.
When MTG is set, this bit when set enables the PWM generator A and the PWM0 and PWM1 pins. When
PWMENA is clear, the PWM generator A is disabled and PWM0 and PWM1 pins are in their inactive states
unless the OUTCTL0 and OUTCTL1 bits are set.
0 PWM generator A and PWM0–1 (2–5 if MTG=0) pins disabled unless the respective OUTCTL bit is set.
1 PWM generator A and PWM0–1 (2–5 if MTG=0) pins enabled.
Load Okay A — When MTG is clear, this bit allows loads of the PRSCA bits, the PMFMODA register and the
PWMVAL0–5 registers into a set of buffers. The buffered prescaler A divisor, PWM counter modulus A value, and
all PWM pulse widths take effect at the next PWM reload.
When MTG is set, this bit allows loads of the PRSCA bits, the PMFMODA register and the PWMVAL0–1 registers
into a set of buffers. The buffered prescaler divisor A, PWM counter modulus A value, PWM0–1 pulse widths take
effect at the next PWM reload.
Set LDOKA by reading it when it is logic zero and then writing a logic one to it. LDOKA is automatically cleared
after the new values are loaded, or can be manually cleared before a reload by writing a logic zero to it. Reset
clears LDOKA.
0 Do not load new modulus A, prescaler A, and PWM0–1 (2–5 if MTG=0) values
1 Load prescaler A, modulus A, and PWM0–1 (2–5 if MTG=0) values
Note: Do not set PWMENA bit before setting the LDOKA bit and do not clear the LDOKA bit at the same time as
PWM Reload Interrupt Enable A — This bit enables the PWMRFA flag to generate CPU interrupt requests.
0 PWMRFA CPU interrupt requests disabled
1 PWMRFA CPU interrupt requests enabled
0
7
setting the PWMENA bit.
= Unimplemented or Reserved
Figure 11-26. PMF Enable Control A Register (PMFENCA)
0
0
6
Table 11-25. PMFENCA Field Descriptions
MC9S12E128 Data Sheet, Rev. 1.07
0
0
5
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
0
0
4
Description
0
0
3
0
0
2
LDOKA
0
1
PWMRIEA
0
0
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