MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 354

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.3.2.31 PMF Frequency Control C Register (PMFFQCC)
Read anytime and write only if MTG is set.
354
Module Base + 0x0031
PWMRFC
LDFQC
PRSCC
HALFC
Reset
Field
7–4
3
2
0
W
R
LDFQC
0000
0001
0010
0011
0100
0101
0110
0111
Load Frequency C — This field selects the PWM load frequency according to
Section 11.4.7.2, “Load Frequency”
Note: The LDFQC field takes effect when the current load cycle is complete, regardless of the state of the load
Half Cycle Reload C — This bit enables half-cycle reloads in center-aligned PWM mode. This bit has no effect
on edge-aligned PWMs.
0 Half-cycle reloads disabled
1 Half-cycle reloads enabled
Prescaler C — This buffered field selects the PWM clock frequency illustrated in
Note: Reading the PRSCC field reads the buffered value and not necessarily the value currently in effect. The
PWM Reload Flag C — This flag is set at the beginning of every reload cycle regardless of the state of the
LDOKC bit. Clear PWMRFC by reading PMFFQCC with PWMRFC set and then writing a logic one to the
PWMRFC bit. If another reload occurs before the clearing sequence is complete, writing logic one to PWMRFC
has no effect.
0 No new reload cycle since last PWMRFC clearing
1 New reload cycle since last PWMRFC clearing
Note: Clearing PWMRFC satisfies pending PWMRFC CPU interrupt requests.
0
7
okay bit, LDOKC. Reading the LDFQC field reads the buffered value and not necessarily the value
currently in effect.
PRSCC field takes effect at the beginning of the next PWM cycle and only when the load okay bit, LDOKC,
is set.
Figure 11-37. PMF Frequency Control C Register (PMFFQCC)
Every 2 PWM opportunities
Every 3 PWM opportunities
Every 4 PWM opportunities
Every 5 PWM opportunities
Every 6 PWM opportunities
Every 7 PWM opportunities
Every 8 PWM opportunities
0
6
PWM Reload Frequency
Every PWM opportunity
LDFQC
Table 11-40. PMFFQCC Field Descriptions
Table 11-41. PWM Reload Frequency C
MC9S12E128 Data Sheet, Rev. 1.07
0
5
for more details.
0
4
Description
LDFQ[3:0]
1000
1001
1010
1011
1100
1101
1110
1111
HALFC
0
3
Every 10 PWM opportunities
Every 11 PWM opportunities
Every 12 PWM opportunities
Every 13 PWM opportunities
Every 14 PWM opportunities
Every 15 PWM opportunities
Every 16 PWM opportunities
Every 9 PWM opportunities
PWM Reload Frequency
0
2
PRSCC
Table
Table
11-41. See
Freescale Semiconductor
11-42.
0
1
PWMRFC
0
0

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