MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 357

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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11.4
11.4.1
A block diagram of the PMF is shown in
generators (A, B, and C) or just a single generator (A). PWM0 and PWM1 constitute Pair A, PWM2 and
PWM3 constitute Pair B, and PWM4 and PWM5 constitute Pair C.
11.4.2
To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by dividing the bus
clock frequency by one, two, four, and eight. Each PWM generator has its own prescaler divisor. Each
prescaler is buffered and will not be used by its PWM generator until the corresponding Load OK bit is set
and a new PWM reload cycle begins.
11.4.3
Each PWM generator contains a 15-bit up/down PWM counter producing output signals with
software-selectables:
11.4.3.1
Each edge-align bit, EDGEx, selects either center-aligned or edge-aligned PWM generator outputs.
Freescale Semiconductor
Alignment—The logic state of each pair EDGE bit determines whether the PWM pair outputs are
edge-aligned or center-aligned
Period—The value written to each pair PWM counter modulo register is used to determine the
PWM pair period. The period can also be varied by using the prescaler
— With edge-aligned output, the modulus is the period of the PWM output in clock cycles
— With center-aligned output, the modulus is one-half of the PWM output period in clock cycles
Pulse width—The number written to the PWM value register determines the pulse width duty cycle
of the PWM output in clock cycles
— With center-aligned output, the pulse width is twice the value written to the PWM value register
— With edge-aligned output, the pulse width is the value written to the PWM value register
Functional Description
Block Diagram
Prescaler
PWM Generator
Alignment
ALIGNMENT REFERENCE
UP/DOWN COUNTER
DUTY CYCLE = 50%
PWM OUTPUT
MODULUS = 4
Figure 11-41. Center-Aligned PWM Output
MC9S12E128 Data Sheet, Rev. 1.07
Figure
11-1. The MTG bit allows the use of multiple PWM
Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
357

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