MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 366

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
11.4.5.2
The IPOLx bits select either the odd or the even PWM value registers to use in the next PWM cycle.
To detect the current status, the voltage on each ISx pin is sampled twice in a PWM period, at the end of
each deadtime. The value is stored in the DTx bits in the PMF Deadtime Sample register (PMFDTMS).
The DTx bits are a timing marker especially indicating when to toggle between PWM value registers.
Software can then set the IPOLx bit to toggle PMFVAL registers according to DTx values.
366
Manual Correction
IPOLx bits are buffered so only one PWM register is used per PWM cycle.
If an IPOLx bit changes during a PWM period, the new value does not take
effect until the next PWM period.
IPOLx bits take effect at the end of each PWM cycle regardless of the state
of the load okay bit, LDOK.
PWM CONTROLLED BY EVEN
PWM CYCLE START
IPOLA
IPOLB
IPOLC
Bit
Figure 11-54. Internal Correction Logic when ISENS = 01
ODD PWMVALREGISTER
PWM CONTROLLED BY
PWMVAL REGISTER
IPOLx BIT
Table 11-48. Top/Bottom Manual Correction
Logic Atate
0
1
0
1
0
1
MC9S12E128 Data Sheet, Rev. 1.07
D
CLK
Q
PMFVAL0 controls PWM0/PWM1 pair
PMFVAL1 controls PWM0/PWM1 pair
PMFVAL2 controls PWM2/PWM3 pair
PMFVAL3 controls PWM2/PWM3 pair
PMFVAL4 controls PWM4/PWM5 pair
PMFVAL5 controls PWM4/PWM5 pair
A
B
NOTE
A/B
GENERATOR
DEADTIME
Output Control
BOTTOM PWM
TOP PWM
Freescale Semiconductor

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