MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 463

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Figure 15-9
target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of
the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the
target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly
drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after
starting the bit time.
Freescale Semiconductor
TARGET SYSTEM
TARGET SYSTEM
SPEEDUP PULSE
TARGET SYS.
START OF BIT TIME
TARGET SYS.
START OF BIT TIME
BKGD PIN
DRIVE AND
BKGD PIN
SPEEDUP
DRIVE TO
BKGD PIN
DRIVE TO
BKGD PIN
CLOCK
CLOCK
PULSE
HOST
PERCEIVED
HOST
PERCEIVED
shows the host receiving a logic 0 from the target. Because the host is asynchronous to the
Figure 15-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 15-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
MC9S12E128 Data Sheet, Rev. 1.07
R-C RISE
10 CYCLES
10 CYCLES
HIGH-IMPEDANCE
HOST SAMPLES
HIGH-IMPEDANCE
HOST SAMPLES
BKGD PIN
BKGD PIN
Chapter 15 Background Debug Module (BDMV4)
SPEEDUP PULSE
HIGH-IMPEDANCE
EARLIEST
START OF
NEXT BIT
EARLIEST
START OF
NEXT BIT
463

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