MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 467

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Figure 15-13
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Because this is
not a probable situation, the protocol does not prevent this conflict from happening.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
Freescale Semiconductor
(TARGET MCU)
BKGD PIN
DRIVES SYNC
TARGET MCU
TO BKGD PIN
BDM CLOCK
DRIVES TO
BKGD PIN
BKGD PIN
HOST
shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
This information is being provided so that the MCU integrator will be aware
that such a conflict could eventually occur.
READ_BYTE
HOST
Figure 15-12. ACK Abort Procedure at the Command Level
AND STARTS TO EXECUTES
READ_BYTE CMD IS ABORTED
Figure 15-13. ACK Pulse and SYNC Request Conflict
THE READ_BYTE CMD
MEMORY ADDRESS
TARGET
BY THE SYNC REQUEST
HOST SYNC REQUEST PULSE
BDM DECODE
ACK PULSE
16 CYCLES
(OUT OF SCALE)
MC9S12E128 Data Sheet, Rev. 1.07
HOST AND
TARGET DRIVE
TO BKGD PIN
AT LEAST 128 CYCLES
NOTE
ELECTRICAL CONFLICT
HIGH-IMPEDANCE
HOST
SYNC RESPONSE
FROM THE TARGET
(OUT OF SCALE)
READ_STATUS
TARGET
Chapter 15 Background Debug Module (BDMV4)
NEW BDM COMMAND
NEW BDM COMMAND
HOST
SPEEDUP PULSE
TARGET
467

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