MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 480

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 16 Debug Module (DBGV1)
16.3.2.1
480
TRGSEL
DBGEN
Reset
BEGIN
Field
ARM
7
6
5
4
W
R
DBGEN
DBG Mode Enable Bit — The DBGEN bit enables the DBG module for use in DBG mode. This bit cannot be
set if the MCU is in secure mode.
0 DBG mode disabled
1 DBG mode enabled
Arm Bit — The ARM bit controls whether the debugger is comparing and storing data in the trace buffer. See
Section 16.4.2.4, “Arming the DBG
0 Debugger unarmed
1 Debugger armed
Note: This bit cannot be set if the DBGEN bit is not also being set at the same time. For example, a write of 01
Trigger Selection Bit — The TRGSEL bit controls the triggering condition for comparators A and B in DBG
mode. It serves essentially the same function as the TAGAB bit in the DBGC2 register does in BKP mode. See
Section 16.4.2.1.2, “Trigger
based on comparator A and B if enabled in DBG mode (DBGBRK = 1). Please refer to
“Breakpoint Based on Comparator A and
0 Trigger on any compare address match
1 Trigger before opcode at compare address gets executed (tagged-type)
Begin/End Trigger Bit — The BEGIN bit controls whether the trigger begins or ends storing of data in the trace
buffer. See
for more details.
0 Trigger at end of stored data
1 Trigger before storing data
Debug Control Register 1 (DBGC1)
0
7
All bits are used in DBG mode only.
This register cannot be written if BKP mode is enabled (BKABEN in
DBGC2 is set).
to DBGEN[7:6] will be interpreted as a write of 00.
= Unimplemented or Reserved
Section 16.4.2.8.1, “Storing with
ARM
0
6
Figure 16-4. Debug Control Register (DBGC1)
Table 16-3. DBGC1 Field Descriptions
TRGSEL
Selection,” for more information. TRGSEL may also determine the type of breakpoint
MC9S12E128 Data Sheet, Rev. 1.07
0
5
Module,” for more information.
B.”
BEGIN
NOTE
NOTE
Begin-Trigger,” and
0
4
Description
DBGBRK
0
3
Section 16.4.2.8.2, “Storing with
0
0
2
Freescale Semiconductor
Section 16.4.3.1,
0
1
CAPMOD
End-Trigger,”
0
0

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