MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 492

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 16 Debug Module (DBGV1)
16.3.2.10 Debug Comparator A Register (DBGCA)
16.3.2.11 Debug Comparator B Extended Register (DBGCBX)
492
EXTCMP
PAGSEL
Reset
Reset
Reset
Field
Field
15:0
15:0
7:6
5:0
W
W
W
R
R
R
Bit 15
Bit 7
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
Table
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively.)
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
15
0
0
0
7
7
Table 16-11
PAGSEL
16-11.
Figure 16-19. Debug Comparator B Extended Register (DBGCBX)
Figure 16-17. Debug Comparator A Register High (DBGCAH)
Figure 16-18. Debug Comparator A Register Low (DBGCAL)
Bit 14
Bit 6
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see
14
0
0
0
6
6
Table 16-22. DBGCBX Field Descriptions
Table 16-21. DBGCA Field Descriptions
Bit 13
Bit 5
MC9S12E128 Data Sheet, Rev. 1.07
13
0
0
0
5
5
Bit 12
Bit 4
12
0
0
0
4
4
Description
Description
Table
16-20.
Bit 11
Bit 3
11
0
0
0
3
3
EXTCMP
Bit 10
Bit 2
10
0
0
0
2
2
Freescale Semiconductor
Bit 9
Bit 1
0
0
0
9
1
1
Table
Bit 8
Bit 0
0
0
0
8
0
0
16-20.