MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 499

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.4.2.5.8
In the inside range trigger mode, if the match condition for A and B happen on the same bus cycle, both
the A and B flags in DBGSC are set and a trigger occurs. If a match condition on only A or only B occurs
no flags are set. If TRGSEL = 1, the inside range is accurate only to word boundaries. If TRGSEL = 0, an
aligned word access which straddles the range boundary will cause a trigger only if the aligned address is
within the range.
16.4.2.5.9
In the outside range trigger mode, if the match condition for A or B is met, the corresponding flag in
DBGSC is set and a trigger occurs. If TRGSEL = 1, the outside range is accurate only to word boundaries.
If TRGSEL = 0, an aligned word access which straddles the range boundary will cause a trigger only if the
aligned address is outside the range.
16.4.2.5.10 Control Bit Priorities
The definitions of some of the control bits are incompatible with each other.
associated with it summarize how these incompatibilities are managed:
Freescale Semiconductor
•
•
•
Read/write comparisons are not compatible with TRGSEL = 1. Therefore, RWAEN and RWBEN
are ignored.
Event-only trigger modes are always considered a begin-type trigger. See
“Storing with
Detail capture mode has priority over the event-only trigger/capture modes. Therefore, event-only
modes have no meaning in detail mode and their functions default to similar trigger modes.
A only
A or B
A then B
Event-only B
A then event-only B
A and B (full mode)
A and not B (full mode)
Inside range
Outside range
1 — Ignored — same as force
2 — Ignored for comparator B
3 — Reduces to effectively “B only”
4 — Works same as A then B
5 — Reduces to effectively “A only” — B not compared
6 — Only accurate to word boundaries
Inside Range (A
Outside Range (address < A or address > B)
Mode
Begin-Trigger,” and
Table 16-25. Resolution of Mode Conflicts
address
MC9S12E128 Data Sheet, Rev. 1.07
Tag
Section 16.4.2.8.2, “Storing with
1
2
5
6
6
5
Normal / Loop1
B)
Force
Tag
1, 3
4
5
5
6
6
End-Trigger.”
Table 16-25
Chapter 16 Debug Module (DBGV1)
Detail
Section 16.4.2.8.1,
Force
and the notes
3
4
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