MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 516

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12E128CPVE
Manufacturer:
FREESCALE
Quantity:
1 560
Part Number:
MC9S12E128CPVE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12E128CPVE
Manufacturer:
FREESCALE
Quantity:
1 560
Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.2
In typical implementations, the MEBI sub-block of the core interfaces directly with external system pins.
Some pins may not be bonded out in all implementations.
Table 18-1
of these pins and associated pull-ups or pull-downs is dependent on the mode of operation and on the
integration of this block at the chip level (chip dependent).
516
BKGD/MODC/
TAGHI
PA7/A15/D15/D7
thru
PA0/A8/D8/D0
PB7/A7/D7
thru
PB0/A0/D0
PE7/NOACC
PE6/IPIPE1/
MODB/CLKTO
.
Pin Name
External Signal Description
outlines the pin names and functions and gives a brief description of their operation reset state
MODC
BKGD
TAGHI
PA7–PA0
A15–A8
D15–D8
D15/D7
thru
D8/D0
PB7–PB0
A7–A0
D7–D0
PE7
NOACC
MODB
PE6
IPIPE1
CLKTO
Pin Functions
Table 18-1. External System Pins Associated With MEBI
MC9S12E128 Data Sheet, Rev. 1.07
At the rising edge on RESET, the state of this pin is registered into the MODC
bit to set the mode. (This pin always has an internal pullup.)
Pseudo open-drain communication pin for the single-wire background debug
mode. There is an internal pull-up resistor on this pin.
When instruction tagging is on, a 0 at the falling edge of E tags the high half of
the instruction word being read into the instruction queue.
General-purpose I/O pins, see PORTA and DDRA registers.
High-order address lines multiplexed during ECLK low. Outputs except in
special peripheral mode where they are inputs from an external tester system.
High-order bidirectional data lines multiplexed during ECLK high in expanded
wide modes, special peripheral mode, and visible internal accesses (IVIS = 1)
in emulation expanded narrow mode. Direction of data transfer is generally
indicated by R/W.
Alternate high-order and low-order bytes of the bidirectional data lines
multiplexed during ECLK high in expanded narrow modes and narrow accesses
in wide modes. Direction of data transfer is generally indicated by R/W.
General-purpose I/O pins, see PORTB and DDRB registers.
Low-order address lines multiplexed during ECLK low. Outputs except in
special peripheral mode where they are inputs from an external tester system.
Low-order bidirectional data lines multiplexed during ECLK high in expanded
wide modes, special peripheral mode, and visible internal accesses (with
IVIS = 1) in emulation expanded narrow mode. Direction of data transfer is
generally indicated by R/W.
General-purpose I/O pin, see PORTE and DDRE registers.
CPU No Access output. Indicates whether the current cycle is a free cycle. Only
available in expanded modes.
At the rising edge of RESET, the state of this pin is registered into the MODB
bit to set the mode.
General-purpose I/O pin, see PORTE and DDRE registers.
Instruction pipe status bit 1, enabled by PIPOE bit in PEAR.
System clock test output. Only available in special modes. PIPOE = 1 overrides
this function. The enable for this function is in the clock module.
Description
Freescale Semiconductor

Related parts for MC9S12E128CPVE