MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 517

• Manufacturer Part Number: MC9S12E128CPVE
• Description: IC MCU 128K FLASH 25MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E128CPVE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: SCI/SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 92
• Number Of Timers: 12
• Operating Supply Voltage: 3.135 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• On-chip Dac: 2-ch x 8-bit
• Controller Family/series: HCS12/S12X
• No. Of I/o's: 90
• Ram Memory Size: 8KB
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: I2C, SCI, SPI
• Rohs Compliant: Yes
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Detailed descriptions of these pins can be found in the device overview chapter.
Freescale Semiconductor
PE5/IPIPE0/MODA
PE4/ECLK
PE3/LSTRB/ TAGLO
PE2/R/W
PE1/IRQ
PE0/XIRQ
PK7/ECS
PK6/XCS
PK5/X19
thru
PK0/X14
Pin Name
Table 18-1. External System Pins Associated With MEBI (continued)
MODA
PE5
IPIPE0
PE4
ECLK
PE3
LSTRB
SZ8
TAGLO
PE2
R/W
PE1
IRQ
PE0
XIRQ
PK7
ECS
PK6
XCS
PK5–PK0
X19–X14
Pin Functions
MC9S12E128 Data Sheet, Rev. 1.07
At the rising edge on RESET, the state of this pin is registered into the MODA
bit to set the mode.
General-purpose I/O pin, see PORTE and DDRE registers.
Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.
General-purpose I/O pin, see PORTE and DDRE registers.
Bus timing reference clock, can operate as a free-running clock at the system
clock rate or to produce one low-high clock per visible access, with the high
period stretched for slow accesses. ECLK is controlled by the NECLK bit in
PEAR, the IVIS bit in MODE, and the ESTR bit in EBICTL.
General-purpose I/O pin, see PORTE and DDRE registers.
Low strobe bar, 0 indicates valid data on D7–D0.
In special peripheral mode, this pin is an input indicating the size of the data
transfer (0 = 16-bit; 1 = 8-bit).
In expanded wide mode or emulation narrow modes, when instruction tagging
is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of
the instruction word being read into the instruction queue.
General-purpose I/O pin, see PORTE and DDRE registers.
Read/write, indicates the direction of internal data transfers. This is an output
except in special peripheral mode where it is an input.
General-purpose input-only pin, can be read even if IRQ enabled.
Maskable interrupt request, can be level sensitive or edge sensitive.
General-purpose input-only pin.
Non-maskable interrupt input.
General-purpose I/O pin, see PORTK and DDRK registers.
Emulation chip select
General-purpose I/O pin, see PORTK and DDRK registers.
External data chip select
General-purpose I/O pins, see PORTK and DDRK registers.
Memory expansion addresses
Chapter 18 Multiplexed External Bus Interface (MEBIV3)
Description
517