MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 549

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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19.3.2.3
Read: Anytime
Write: The EEON bit can be written to any time on all devices. Bits E[11:15] are “write anytime in all
modes” on most devices. On some devices, bits E[11:15] are “write once in normal and emulation modes
and write anytime in special modes”. See device overview chapter to determine the actual write access
rights.
This register initializes the position of the internal EEPROM within the on-chip system memory map.
Freescale Semiconductor
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the
EE[15:11]
Reset
actual reset state of this register.
EEON
Field
7:3
0
W
R
1
EE15
Internal EEPROM Map Position — These bits determine the upper five bits of the base address for the system’s
internal EEPROM array.
Enable EEPROM — This bit is used to enable the EEPROM memory in the memory map.
0 Disables the EEPROM from the memory map.
1 Enables the EEPROM in the memory map at the address selected by EE[15:11].
Initialization of Internal EEPROM Position Register (INITEE)
7
Writes to this register take one cycle to go into effect.
Figure 19-5. Initialization of Internal EEPROM Position Register (INITEE)
= Unimplemented or Reserved
EE14
6
Table 19-4. INITEE Field Descriptions
EE13
MC9S12E128 Data Sheet, Rev. 1.07
5
EE12
NOTE
4
Description
EE11
3
Chapter 19 Module Mapping Control (MMCV4)
0
2
0
1
EEON
0
549

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