MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 554

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Chapter 19 Module Mapping Control (MMCV4)
19.3.2.9
Read: Anytime
Write: Determined at chip integration. Generally it’s: “write anytime in all modes;” on some devices it will
be: “write only in special modes.” Check specific device documentation to determine which applies.
Reset: Defined at chip integration as either 0x00 (paired with write in any mode) or 0x3C (paired with
write only in special modes), see device overview chapter.
554
1. The reset state of this register is controlled at chip integration. Please refer to the device overview section to determine the
Reset
actual reset state of this register.
W
R
1
Program Page Index Register (PPAGE)
0
7
As stated, the bits in this register provide read visibility to the system
memory space and on-chip/off-chip partitioning allocations defined at
system integration. The actual array size for any given type of memory
block may differ from the allocated size. Please refer to the device overview
chapter for actual sizes.
NOTES:
1. The ROMHM software bit in the MISC register determines the accessibility of the
FLASH/ROM memory space. Please refer to
1
(MEMSIZ1),” for a detailed functional description of the ROMHM bit.
pag_sw1:pag_sw0
= Unimplemented or Reserved
Table 19-11. Allocated FLASH/ROM Physical Memory Space
rom_sw1:rom_sw0
0
6
00
01
10
11
Figure 19-11. Program Page Index Register (PPAGE)
Table 19-12. Allocated Off-Chip Memory Options
00
01
10
11
PIX5
MC9S12E128 Data Sheet, Rev. 1.07
5
Off-Chip Space
876K bytes
768K bytes
512K bytes
PIX4
NOTE
0K byte
4
Section 19.3.2.8, “Memory Size Register
PIX3
3
Allocated FLASH
or ROM Space
48K bytes
64K bytes
16K bytes
0K byte
On-Chip Space
128K bytes
256K bytes
512K bytes
PIX2
1M byte
2
(1)
(1)
Freescale Semiconductor
PIX1
1
PIX0
0

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