MC9S12E128CPVE Freescale Semiconductor, MC9S12E128CPVE Datasheet - Page 578

IC MCU 128K FLASH 25MHZ 112-LQFP

MC9S12E128CPVE

Manufacturer Part Number
MC9S12E128CPVE
Description
IC MCU 128K FLASH 25MHZ 112-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheets

Specifications of MC9S12E128CPVE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
91
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
SCI/SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
92
Number Of Timers
12
Operating Supply Voltage
3.135 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
2-ch x 8-bit
Controller Family/series
HCS12/S12X
No. Of I/o's
90
Ram Memory Size
8KB
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Appendix A Electrical Characteristics
The loop bandwidth f
typical values are 50. = 0.9 ensures a good transient response.
And finally the frequency relationship is defined as
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f
The capacitance C
The capacitance C
A.3.3.2
The basic functionality of the PLL is shown in
deviation from the reference clock f
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in
578
C
=10kHz:
f
C
<
------------------------------------------
R
2
Jitter Information
=
+
C
2
---------------------------- -
s
p
s
can now be calculated as:
should be chosen in the range of:
1
f
C
ref
=
+
K
should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
n
--------------------- -
n f
2
2
=
C
f
s
C
C
f
-------------
----- -
10
1
VCO
f
2
20 C
ref
R
= 2* *50*10kHz/(316.7Hz/ )=9.9k =~10k
ref
MC9S12E128 Data Sheet, Rev. 1.07
f
is measured and input voltage to the VCO is adjusted
=
f
0.516
-------------- -
f
C
C
C
p
<
2
< 25kHz
R
------------ -
4 10
f
C
ref
;
Figure
synr
s
=
;
10
0.9
A-2. With each transition of the clock f
+
=
1
0.9
C
p
= 5.19nF =~ 4.7nF
= 470pF
= 50
Freescale Semiconductor
Figure
cmp
A-3.
, the

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