MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 435
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MC9S12NE64VTU
Manufacturer Part Number
MC9S12NE64VTU
Description
IC MCU 25MHZ ETHERNET/PHY 80TQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64VTU
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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The HCS12 core architecture limits the physical address space available to 64K bytes. The program page
index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six
page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF
as defined in
without using the address bus.
16.4
The MMC sub-block performs four basic functions of the core operation: bus control, address decoding
and select signal generation, memory expansion, and security decoding for the system. Each aspect is
described in the following subsections.
16.4.1
The MMC controls the address bus and data buses that interface the core with the rest of the system. This
includes the multiplexing of the input data buses to the core onto the main CPU read data bus and control
Freescale Semiconductor
PIX[5:0]
Field
5:0
Functional Description
Bus Control
Table
Program Page Index Bits 5:0 — These page index bits are used to select which of the 64 FLASH or ROM
array pages is to be accessed in the program page window as shown in
Normal writes to this register take one cycle to go into effect. Writes to this
register using the special access of the CALL and RTC instructions will be
complete before the end of the associated instruction.
PIX5
0
0
0
0
1
1
1
1
.
.
.
.
.
16-14. CALL and RTC instructions have special access to read and write this register
PIX4
0
0
0
0
1
1
1
1
.
.
.
.
.
Table 16-14. Program Page Index Register Bits
Table 16-13. MEMSIZ0 Field Descriptions
PIX3
0
0
0
0
1
1
1
1
.
.
.
.
MC9S12NE64 Data Sheet, Rev. 1.1
PIX2
0
0
0
0
1
1
1
1
.
.
.
.
.
NOTE
PIX1
Description
0
0
1
1
0
0
1
1
.
.
.
.
.
PIX0
0
1
0
1
0
1
0
1
.
.
.
.
.
Program Space
16K page 60
16K page 61
16K page 62
16K page 63
Table
16K page 0
16K page 1
16K page 2
16K page 3
Selected
.
.
.
.
.
16-14.
Functional Description
435
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