MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 100

IC MCU 256K FLASH 80-QFP

MC9S12XDT256CAA

Manufacturer Part Number
MC9S12XDT256CAA
Description
IC MCU 256K FLASH 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XDT256CAA

Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
59
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Processor Series
S12XD
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
59
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12XDT256CAA
Manufacturer:
FREESCALE
Quantity:
6 540
Part Number:
MC9S12XDT256CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 2 Clocks and Reset Generator (S12CRGV6)
The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1):
The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
the maximum system frequency (f
manual mode:
2.4.1.2
100
EXTAL
XTAL
The TRACK bit is a read-only indicator of the mode of the filter.
The TRACK bit is set when the VCO frequency is within a certain tolerance,
the VCO frequency is out of a certain tolerance,
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance,
when the VCO frequency is out of a certain tolerance,
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in
manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode.
After turning on the PLL by setting the PLLON bit software must wait a given time (t
entering tracking mode (ACQ = 0).
After entering tracking mode software must wait a given time (t
as the source for system and core clocks (PLLSEL = 1).
CONDITION
OSCILLATOR
GATING
System Clocks Generator
= CLOCK GATE
PHASE
LOCK
LOOP
OSCCLK
PLLCLK
MONITOR
CLOCK
Figure 2-17. System Clocks Generator
sys
PLLSEL or SCM
MC9S12XDP512 Data Sheet, Rev. 2.21
) and require fast start-up. The following conditions apply when in
1
0
1
0
SCM
STOP(PSTP,PCE),
STOP(PSTP,PRE),
WAIT(COPWAI),
WAIT(RTIWAI),
COP ENABLE
RTI ENABLE
SYSCLK
STOP
unt
STOP
.
unl
.
2
al
) before selecting the PLLCLK
CLOCK PHASE
GENERATOR
COP
RTI
Freescale Semiconductor
trk
Lock
, and is clear when
, and is cleared
acq
CORE CLOCK
BUS CLOCK
OSCILLATOR
CLOCK
) before

Related parts for MC9S12XDT256CAA