MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 1014

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.42 Port H Data Register (PTH)
Read: Anytime.
Write: Anytime.
Port H pins 7–0 are associated with the routed SPI1.
These pins can be used as general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
The routed SPI1 function takes precedence over the general purpose I/O function if the routed SPI1 is
enabled. Refer to SPI section for details.
24.0.5.43 Port H Input Register (PTIH)
Read: Anytime.
Write: Never, writes to this register have no effect.
1016
Routed
PIFP[7:0]
Reset
Reset
Field
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
7–0
SPI
W
W
associated pin values.
R
R
1
PTIH7
PTH7
Interrupt Flags Port P
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
—
0
7
7
Writing a logic level “1” clears the associated flag.
= Unimplemented or Reserved
PTIH6
PTH6
—
0
6
6
Figure 24-45. Port H Input Register (PTIH)
Figure 24-44. Port H Data Register (PTH)
Table 24-40. PIFP Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PTIH5
PTH5
—
0
5
5
PTIH4
PTH4
—
0
4
4
Description
PTIH3
PTH3
SS1
—
0
3
3
PTIH2
SCK1
PTH2
—
0
2
2
Freescale Semiconductor
MOSI1
PTIH1
PTH1
—
0
1
1
MISO1
PTIH0
PTH0
—
0
0
0